august 1999 6-1 pin configurations pin names a 0 - a 16 address inputs w write enable dq 0 - dq 7 data in/out e chip enable g output enable v cc power (+ 5v) v ss ground a 13 a 8 a 9 a 11 nc a 16 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss v cc a 15 w a 10 e dq 7 dq 6 dq 5 dq 4 dq 3 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a 14 v cc a 15 g a 10 e dq 7 dq 6 dq 5 dq 4 dq 3 nc STK25CA8 128k x 8 autostore ? nvsram quantumtrap ? cmos nonvolatile static ram module features ? nonvolatile storage without battery problems ? directly replaces 128k x 8 static ram, battery- backed ram or eeprom ? 35ns and 45ns access times ? store to eeprom initiated by autostore ? on power down ? recall to sram on power restore ? 22ma i cc at 200ns cycle time ? unlimited read, write and recall cycles ? 1,000,000 store cycles to eeprom ? 100-year data retention over full commercial temperature range ? commercial and industrial temperatures ? 32-pin 600 mil dual in-line module description the simtek STK25CA8 is a fast static ram with a nonvolatile, electrically erasable prom element incorporated in each static memory cell. the sram can be read and written an unlimited number of times, while independent nonvolatile data resides in the eeprom . data transfers from the sram to the eeprom (the store operation) can take place auto- matically on power down using charge stored in sys- tem capacitance. transfers from the eeprom to the sram (the recall operation) take place automati- cally on restoration of power. block diagram a 6 a 7 a 2 column i/o column dec static ram array 512 x 512 row decoder input buffers eeprom array 512 x 512 store/ recall control power control a 11 a 12 a 13 a 14 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 v cc g e w a 9 a 8 a 10 a 3 a 0 a 1 a 4 a 5 a 15 a 16 module decoder 512 x 512 store recall 32 - 600 mil dual in-line module
STK25CA8 august 1999 6-2 absolute maximum ratings a voltage on input relative to v ss . . . . . . . . . . C0.6v to (v cc + 0.5v) voltage on dq 0-7 . . . . . . . . . . . . . . . . . . . . . . C0.5v to (v cc + 0.5v) temperature under bias . . . . . . . . . . . . . . . . . . . . . C55 c to 125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . C65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w dc output current (1 output at a time, 1s duration) . . . . . . . . 15ma dc characteristics (v cc = 5.0v 10%) note b: i cc 1 and i cc 3 are dependent on output loading and cycle rate. the speci?ed values are obtained with outputs unloaded. note c: i cc 2 and i cc 4 are the average currents required for the duration of the respective store cycles (t store ). note d: e 3 v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. ac test conditions capacitance e (t a = 25 c, f = 1.0mhz) note e: these parameters are guaranteed but not tested. symbol parameter commercial industrial units notes min max min max i cc 1 b average v cc current 140 125 150 133 ma ma t avav = 35ns t avav = 45ns i cc 2 c average v cc current during store 20 25 ma all inputs dont care, v cc = max i cc 3 b average v cc current at t avav = 200ns 22 25 ma w 3 (v cc C 0.2v) all others cycling, cmos levels i cc 4 c average v cc current during autostore ? cycle 18 20 ma all inputs dont care i sb d v cc standby current (standby, stable cmos input levels) 99ma e 3 (v cc C 0.2v) all others v in 0.2v or 3 (v cc C 0.2v) i ilk input leakage current 2 2 m a v cc = max v in = v ss to v cc i olk off-state output leakage current 10 10 m a v cc = max v in = v ss to v cc , e or g 3 v ih v ih input logic 1 voltage 2.2 v cc + .5 2.2 v cc + .5 v all inputs v il input logic 0 voltage v ss C .5 0.8 v ss C .5 0.8 v all inputs v oh output logic 1 voltage 2.4 2.4 v i out = C 4ma v ol output logic 0 voltage 0.4 0.4 v i out = 8ma t a operating temperature 0 70 C40 85 c input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 3v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels . . . . . . . . . . . . . . . 1.5v output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see figure 1 symbol parameter max units conditions c in input capacitance 20 pf d v = 0 to 3v c out output capacitance 28 pf d v = 0 to 3v figure 1: ac output loading 480 ohms 30 pf 255 ohms 5.0v including output scope and fixture note a: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at condi- tions above those indicated in the operational sections of this speci?cation is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability.
STK25CA8 august 1999 6-3 sram read cycles #1 & #2 (v cc = 5.0v 10%) note f: w must be high during sram read cycles and low during sram write cycles. note g: i/o state assumes e, g, < v il and w > v ih ; device is continuously selected. note h: measured + 200mv from steady state output voltage. sram read cycle #1: address controlled f, g sram read cycle #2: e controlled f no. symbols parameter STK25CA8-35 STK25CA8-45 units #1, #2 alt. min max min max 1t elqv t acs chip enable access time 35 45 ns 2t avav f t rc read cycle time 35 45 ns 3t avqv g t aa address access time 35 45 ns 4t glqv t oe output enable to data valid 15 20 ns 5t axqx g t oh output hold after address change 5 5 ns 6t elqx t lz chip enable to output active 5 5 ns 7t ehqz h t hz chip disable to output inactive 13 15 ns 8t glqx t olz output enable to output active 0 0 ns 9t ghqz h t ohz output disable to output inactive 13 15 ns 10 t elicch e t pa chip enable to power active 0 0 ns 11 t ehiccl d, e t ps chip disable to power standby 35 45 ns data valid 5 t axqx 3 t avqv dq (data out) address 2 t avav 6 t elqx standby data valid 8 t glqx 4 t glqv dq (data out) e address 2 t avav g i cc active 1 t elqv 10 t elicch 11 t ehiccl 7 t ehqz 9 t ghqz
STK25CA8 august 1999 6-4 sram write cycles #1 & #2 (v cc = 5.0v 10%) note i: if w is low when e goes low, the outputs remain in the high-impedance state. note j: e or w must be 3 v ih during address transitions. sram write cycle #1 : w controlled j sram write cycle #2 : e controlled j no. symbols parameter STK25CA8-35 STK25CA8-45 units #1 #2 alt. min max min max 12 t avav t avav t wc write cycle time 35 45 ns 13 t wlwh t wleh t wp write pulse width 25 30 ns 14 t elwh t eleh t cw chip enable to end of write 25 30 ns 15 t dvwh t dveh t dw data set-up to end of write 12 15 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 25 30 ns 18 t avwl t avel t as address set-up to start of write 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 ns 20 t wlqz h, i t wz write enable to output disable 13 15 ns 21 t whqx t ow output active after end of write 5 5 ns previous data data out e address 12 t avav w 16 t whdx data in 1 9 t whax 13 t wlwh 18 t avwl 17 t avwh data valid 20 t wlqz 15 t dvwh high impedance 21 t whqx 14 t elwh data out e address 12 t avav w data in 13 t wleh 17 t aveh data valid high impedance 14 t eleh 18 t avel 15 t dveh 19 t ehax 16 t ehdx
STK25CA8 august 1999 6-5 autostore ?/power-up recall (v cc = 5.0v 10%) note k: t restore starts from the time v cc rises above v switch . autostore ?/power-up recall no. symbols parameter STK25CA8 units notes standard min max 22 t restore power-up recall duration 550 m sk 23 t store store cycle duration 10 ms g 24 t delay time allowed to complete sram cycle 1 m sg 25 v switch low voltage trigger level 4.0 4.5 v 26 v reset low voltage reset level 3.9 v v cc v switch v reset power-up recall w dq (data out) autostore ? 5v 22 t restore 24 t delay 23 t store 25 26 power-up recall brown out autostore ? no recall (v cc did not go below v reset ) brown out autostore ? recall when v cc returns above v switch brown out no store due to no sram writes no recall (v cc did not go below v reset )
STK25CA8 august 1999 6-6 the STK25CA8 is a versatile memory module that provides two modes of operation. the STK25CA8 can operate as a standard 128k x 8 sram . it has a 128k x 8 eeprom shadow to which the sram infor- mation can be copied, or from which the sram can be updated in nonvolatile mode. noise considerations note that the STK25CA8 is a high-speed memory and so must have a high frequency bypass capaci- tor of approximately 0.1 m f connected between v cc and v ss , using leads and traces that are as short as possible. as with all high-speed cmos ics, normal careful routing of power, ground and signals will help prevent noise problems. sram read the STK25CA8 performs a read cycle whenever e and g are low and w is high. the address speci?ed on pins a 0-16 determines which of the 131,072 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t avqv ( read cycle #1). if the read is initiated by eor g, the outputs will be valid at t elqv or at t glqv , whichever is later ( read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time without the need for tran- sitions on any control input pins, and will remain valid until another address change or until eor gis brought high. sram write a write cycle is performed whenever e and w are low. the address inputs must be stable prior to entering the write cycle and must remain stable until either eor w goes high at the end of the cycle. the data on the common i/o pins dq 0-7 will be writ- ten into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write . it is recommended that g be kept high during the entire write cycle to avoid data bus contention on the common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. autostore ? operation the STK25CA8 uses the intrinsic system capaci- tance to perform an automatic store on power down. as long as the system power supply takes at least t store to decay from v switch down to 3.6v the STK25CA8 will safely and automatically store the sram data in eeprom on power down. in order to prevent unneeded store operations, automatic store s will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. power-up recall during power up, or after any low-power condition (v cc STK25CA8 is in a write state at the end of power-up recall , the sram data will be corrupted. to help avoid this situation, a 10k ohm resistor should be connected either between w and system v cc or between e and system v cc . hardware protect the STK25CA8 offers hardware protection against inadvertent store operation and sram write s dur- ing low-voltage conditions. when v cap STK25CA8 draws signi?cantly less current when it is cycled at times longer than 50ns. if the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. the overall average current drawn by the STK25CA8 depends on the following items: 1) cmos vs. ttl input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of read sto write s; 5) the operating temperature; 6) the v cc level; and 7) i/o loading. device operation
STK25CA8 august 1999 6-7 ordering information temperature range blank = commercial (0 to 70?c) i = industrial (C40 to 85?c ) access time 35 = 35ns 45 = 45ns package d = 32-pin 600 mil dual in-line module - d 45 i STK25CA8
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